Formal verification of NCL circuits
Formal verification of NCL circuits
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NCL 电路的形式化验证
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
S. Srinivasan
中科院分区：
文献类型：
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作者：
Ashiq A. Sakib;S. Le;S. Smith;S. Srinivasan
在这一章中，作者描述了空约定逻辑（NCL）电路的等价性检验方法。请注意，目前还没有针对准延迟不敏感（QDI）电路的商用等效检查器。对于商业应用，NCL电路和一般的QDI电路通常由同步知识产权设计合成。然后可以进一步优化和修补所得到的NCL设计。因此，作者设计了一个等价性检验器，它可以用于两种情况：（1）验证两个NCL设计的功能等价性;（2）验证NCL设计与同步设计之间的等价性。
In this chapter, the author describe an equivalence checking methodology for NULL Convention Logic (NCL) circuits. Note that currently, there are no commercial equivalence checkers for quasi-delay insensitive (QDI) circuits. For commercial applications, NCL circuits, and QDI circuits in general, are often synthesized from synchronous intellectual property designs. The resulting NCL design may then be further optimized and tinkered with. Therefore, the author have designed an equivalence checker that can be used in two ways: (1) to verify the functional equivalence of two NCL designs and (2) to verify the equivalence between an NCL design and a synchronous design.