On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
复制标题
边界扫描中嵌入时间数字转换器检测延迟故障
DOI：
10.1587/transinf.e96.d.1986
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
Masaki Hashizume
中科院分区：
文献类型：
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作者：
H. Yotsuyanagi;H. Makimoto;Takanobu Nimiya;Masaki Hashizume
摘要本文提出了一种测试延迟故障的方法，其中一个数字转换器（TDC）嵌入了从其他内核或芯片的转换修改了TDC电路，以设置延迟线的初始值，因为还研究了测量两个或更多路径的正时休息的条件。在我们的边界扫描电路中的TDC延迟线中可能发生。用于tdc和边界扫描的实验IC，并测量以估计由嵌入边界扫描单元中的TDC测量的一些路径的延迟。还显示了具有边界扫描电路的基准电路，即即使信号在TDC中重叠，也可以观察到多个路径的正时松弛。
SUMMARY This paper proposes a method for testing delay faults us-ing a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.