Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs
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DOI：
10.1145/3174243.3174255
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发表时间：
2018-02
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通讯作者：
Yuan Zhou;Udit Gupta;Steve Dai;Ritchie Zhao;Nitish Kumar Srivastava;Hanchen Jin;Joseph Featherston;Yi-Hsiang Lai;Gai Liu;Gustavo Angarita Velasquez;Wenping Wang;Zhiru Zhang
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作者：
Yuan Zhou;Udit Gupta;Steve Dai;Ritchie Zhao;Nitish Kumar Srivastava;Hanchen Jin;Joseph Featherston;Yi-Hsiang Lai;Gai Liu;Gustavo Angarita Velasquez;Wenping Wang;Zhiru Zhang
现代高级综合 (HLS) 工具大大缩短了设计和实现基于 FPGA 的复杂加速器的周转时间。它们还暴露了各种优化机会，这些优化机会在寄存器传输级别上无法轻易探索。随着 HLS 设计方法的日益普及和综合优化的不断进步，越来越需要现实的基准来 (1) 促进工具之间的比较，(2) 评估和压力测试新的综合技术，以及 (3) 建立有意义的性能基线来跟踪 HLS 技术的进展。虽然已经存在多个 HLS 基准测试套件，但它们主要由教科书式的小型函数内核组成，而不是完整且复杂的应用程序。为了解决这一限制，我们推出了 Rosetta，这是一个针对软件可编程 FPGA 的现实基准测试套件。 Rosetta 中的设计是完全开发的应用程序。它们与现实的性能约束相关联，并利用现代 HLS 工具的高级功能进行优化。我们相信，Rosetta 不仅对 HLS 研究社区有用，而且还可以作为非 HLS 专家用户的一套设计教程。在本文中，我们描述了基准测试的特征以及应用于它们的优化技术。我们进一步报告了嵌入式 FPGA 设备以及云 FPGA 平台上的实验结果。
Modern high-level synthesis (HLS) tools greatly reduce the turn-around time of designing and implementing complex FPGA-based accelerators. They also expose various optimization opportunities, which cannot be easily explored at the register-transfer level. With the increasing adoption of the HLS design methodology and continued advances of synthesis optimization, there is a growing need for realistic benchmarks to (1) facilitate comparisons between tools, (2) evaluate and stress-test new synthesis techniques, and (3) establish meaningful performance baselines to track progress of the HLS technology. While several HLS benchmark suites already exist, they are primarily comprised of small textbook-style function kernels, instead of complete and complex applications. To address this limitation, we introduce Rosetta, a realistic benchmark suite for software programmable FPGAs. Designs in Rosetta are fully-developed applications. They are associated with realistic performance constraints, and optimized with advanced features of modern HLS tools. We believe that Rosetta is not only useful for the HLS research community, but can also serve as a set of design tutorials for non-expert HLS users. In this paper we describe the characteristics of our benchmarks and the optimization techniques applied to them. We further report experimental results on an embedded FPGA device as well as a cloud FPGA platform.