Experimental verification of electrostatic boundary conditions in gate-patterned quantum devices
Experimental verification of electrostatic boundary conditions in gate-patterned quantum devices
复制标题
门图案量子器件静电边界条件的实验验证
DOI：
10.1088/1361-6463/aac376
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
C. Ford
中科院分区：
文献类型：
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作者：
H. Hou;Y. Chung;G. Rughoobur;T. Hsiao;A. Nasir;A. Flewitt;J. Griffiths;I. Farrer;D. Ritchie;C. Ford
在门图型量子器件的模型中，选择正确的静电边界条件（BCs）以匹配实验是非常重要的。在这项研究中，我们在掺杂和未掺杂的GaAs异质结构中模拟了各种bc的门控图案器件。栅极之间的无约束表面，其上有介电区和表面电荷的冻结层，以及非常深的后边界，获得了最佳匹配。实验中，我们发现在ZnO覆盖层蚀刻前后，掺杂异质结构中1D通道的掐断特性有~ 0.2 V的偏移，与模型预测的一致。此外，我们还观察到由表面声波通过未掺杂异质结构中的横向诱导n-i-n结驱动的清晰量子化电流。在模型中，在这种类型的设备中泵送电子的能力对后面的BC高度敏感。利用改进的边界条件，可以很容易地使用标准软件对量子器件进行相当精确的建模。
In a model of a gate-patterned quantum device, it is important to choose the correct electrostatic boundary conditions (BCs) in order to match experiment. In this study, we model gated-patterned devices in doped and undoped GaAs heterostructures for a variety of BCs. The best match is obtained for an unconstrained surface between the gates, with a dielectric region above it and a frozen layer of surface charge, together with a very deep back boundary. Experimentally, we find a ∼0.2 V offset in pinch-off characteristics of 1D channels in a doped heterostructure before and after etching off a ZnO overlayer, as predicted by the model. Also, we observe a clear quantised current driven by a surface acoustic wave through a lateral induced n-i-n junction in an undoped heterostructure. In the model, the ability to pump electrons in this type of device is highly sensitive to the back BC. Using the improved boundary conditions, it is straightforward to model quantum devices quite accurately using standard software.