Logic Locking With Provable Security Against Power Analysis Attacks

Logic Locking With Provable Security Against Power Analysis Attacks
复制标题

逻辑锁定具有可证明的安全性,可抵御功率分析攻击

DOI:
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发表时间:
2020
影响因子:
2.9
通讯作者:
O. Sinanoglu
O. Sinanoglu
中科院分区:
计算机科学3区
文献类型:
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作者:
A. Sengupta;Bodhisatwa Mazumdar;Muhammad Yasin;O. Sinanoglu

文献摘要

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将集成电路(IC)制造外包给外部代工厂导致了许多新的安全漏洞,包括IC盗版、过度建造和逆向工程。在这方面,引入了逻辑锁定(LL)来保护知识产权免受此类威胁。在本文中,我们评估各种LL技术的强度,包括早期的作品,如随机LL(RLL)和基于故障分析的LL(FLL),对基于功率的侧信道攻击。我们已经开发了攻击,其中至少60%的关键位可以成功地恢复为60%的电路RLL和FLL使用32位的密钥。然而,当使用64位密钥时,RLL和FLL的成功率分别降低到45%和35%。我们证明了我们提出的攻击的实用性,通过安装它对RLL和FLL实现的ISCAS'85和MCNC基准电路斯巴达-6 FPGA平台。此外,我们提出了差分功率分析(DPA)结果的互信息分析LL技术,捕获任何依赖之间的中间数据和捕获的功率迹线。我们还正式建立了基于可满足性(SAT)攻击的弹性意味着对DPA攻击的弹性以及LL技术。我们进一步验证了这一点,通过实验斯巴达-6 FPGA上的SAKURA-G开发板上的最近LL技术,是已知的,以挫败SAT攻击。
Outsourcing of integrated circuit (IC) fabrication to external foundries has lead to many new security vulnerabilities, including IC piracy, overbuilding, and reverse engineering. In this regard, logic locking (LL) was introduced to protect intellectual property from such threats. In this paper, we evaluate the strength of various LL techniques, including earlier works, such as random LL (RLL) and fault analysis-based LL (FLL), against power-based side-channel attack. We have developed attacks where at least 60% of the key bits can be successfully recovered for 60% of the circuits for both RLL and FLL using a 32-bit key. However, the success rate reduces to 45% and 35% for RLL and FLL, respectively, when using a 64-bit key. We demonstrate the practicality of our proposed attack by mounting it against RLL and FLL implementations of ISCAS’85 and MCNC benchmark circuits on Spartan-6 FPGA platform. Further, we present differential power analysis (DPA) results on mutual information analysis on LL techniques that capture any dependence between the intermediate data and the captured power traces. We also formally establish that resilience to satisfiability-based (SAT) attack implies resilience to DPA attack as well for an LL technique. We validate this further via experiments on Spartan-6 FPGA on SAKURA-G development board for a recent LL technique that is known to thwart the SAT attack.