Architectural Support For Translation Table Management In Large Address Space Machines
Architectural Support For Translation Table Management In Large Address Space Machines
复制标题
大地址空间机器中翻译表管理的架构支持
DOI：
10.1109/isca.1993.698544
复制
发表时间：
1993
期刊：
影响因子：
--
通讯作者：
Jim Hays
中科院分区：
文献类型：
--
作者：
Jerome C. Huck;Jim Hays
虚拟存储器页转换表提供从虚拟地址到物理地址的映射。当硬件控制的转换后备缓冲器（TLB）不包含转换时，这些表提供转换。这些表的结构和管理方法从完全硬件实现到完全基于软件的算法都有所不同。
进程使用的虚拟地址空间的大小正在迅速增长，超过32位地址。随着使用的地址空间的增加，新的问题和问题浮出水面。管理页转换表的传统方法不适用于大地址空间体系结构。
这里描述的散列页表（HPT）提供了一种非常快速和空间高效的转换表，通过在硬件和软件之间划分TLB管理责任来减少开销。测量表明，它适用于各种操作系统和工作负载，特别是大型虚拟地址空间机器。在超过40亿条指令的模拟中，观察到了5%到10%的改进。
Virtual memory page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Translation Lookaside Buffers (TLBs) do not contain a translation, these tables provide the translation. Approaches to the structure and management of these tables vary from full hardware implementations to complete software based algorithms.
The size of the virtual address space used by processes is rapidly growing beyond 32 bits of address. As the utilized address space increases, new problems and issues surface. Traditional methods for managing the page translation tables are inappropriate for large address space architectures.
The Hashed Page Table (HPT), described here, provides a very fast and space efficient translation table that reduces overhead by splitting TLB management responsibilities between hardware and software. Measurements demonstrate its applicability to a diverse range of operating systems and workloads and, in particular, to large virtual address space machines. In simulations of over 4 billion instructions, improvement of 5 to 10% were observed.