An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
复制标题
DOI：
10.1145/3593807
复制
发表时间：
2023-05
影响因子：
1.4
通讯作者：
Yijun Cui;Jiang Li;Yunpeng Chen;Chenghua Wang;Chongyan Gu;Máire O’Neill;Weiqiang Liu
中科院分区：
文献类型：
--
作者：
Yijun Cui;Jiang Li;Yunpeng Chen;Chenghua Wang;Chongyan Gu;Máire O’Neill;Weiqiang Liu
环形振荡器（RO）PUF可以在不同的FPGA平台上实现，具有高度的唯一性和可靠性。为了降低传统RO PUF的硬件成本，提出了一种使用可编程延迟单元的新设计，即PRO PUF。可编程延迟单元的可编程互连点（PIP）用于增强可配置性。所提出的设计的PUF单元能够通过调整延迟单元的传播路径在任何阶段被有效地编程为RO PUF。所提出的 PRO PUF 可以生成大量响应，同时消耗更少的硬件资源。为了验证性能，所提出的设计已在 Xilinx FPGA 上实现，并使用标准 40nm 技术进行模拟。实验结果表明，所提出的设计具有较高的独特性、可靠性和硬件效率。此外，PRO PUF 已使用机器学习攻击（CMA-ES 攻击）进行了评估。结果表明，与传统的 RO 相关 PUF 设计相比，所提出的结构更能抵抗常见的建模攻击。
The ring oscillator (RO) PUF can be implemented on different FPGA platforms with high uniqueness and reliability. To decrease the hardware cost of conventional RO PUFs, a new design using the programmable delay units is proposed, namely, PRO PUF. The programmable interconnect points (PIPs) of programmable delay units are used to enhance the configurability. The PUF cell of the proposed design has the ability to be efficiently programmed to an RO PUF at any stage by adjusting the propagation paths of the delay units. A significant number of responses can be generated by the proposed PRO PUF while consuming fewer hardware resources. To verify the performance, the proposed design has been implemented on Xilinx FPGAs and also simulated using a standard 40nm technology. The experimental results have shown that the proposed design achieves high uniqueness, reliability, and hardware efficiency. Moreover, the PRO PUF has been evaluated using a machine learning attack, the CMA-ES attack. The results have shown that the proposed structure is more resistant to common modeling attacks when compared to conventional RO-related PUF designs.