An efficient multi-rate LDPC-CC decoder with layered decoding algorithm
An efficient multi-rate LDPC-CC decoder with layered decoding algorithm
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DOI：
10.1109/icc.2013.6655475
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发表时间：
2013-06
期刊：
影响因子：
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通讯作者：
Yun Chen;Changsheng Zhou;Yuebin Huang;Xiaoyang Zeng
中科院分区：
文献类型：
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作者：
Yun Chen;Changsheng Zhou;Yuebin Huang;Xiaoyang Zeng
本文提出了一种高效的多速率低密度奇偶校验卷积码译码器。将分层译码算法引入到LDPC-CC译码中。仿真结果表明，在较少处理器的情况下，该方法可以获得比原有的短传播算法更好的性能。此外，本文还提出了一种新的专用集成电路结构，该结构采用所提出的算法，可以支持IEEE1901标准中所有码率(1/2、2/3、3/4、4/5)的LDPC-CC码。基于中芯国际130nmCMOS工艺，我们的解码器在200MHz时的最大吞吐量达到了333.3 Mb/S。核心面积为3.55mm2，有10个处理器。在码率为4/5、频率为200 MHz时，平均功耗为262 mW。VLSI测试结果表明，该解码器具有较高的存储效率和面积效率。
An efficient multi-rate Low-Density Parity-Check Convolutional Code decoder will be present in this paper. We will introduce layered decoding algorithm into LDPC-CC decoding. Simulation results shows that our method can achieve better performance than the original brief propagation algorithm with less processors. Besides a new ASIC architecture which adopt proposed algorithm and can support all code rate (1/2, 2/3, 3/4, 4/5) of the LDPC-CC code in IEEE 1901 is proposed. Based on SMIC 130 nm CMOS process, our decoder attaints a maximum throughput of 333.3 Mb/s at 200 MHz. The core area is 3.55 mm2 with 10 processors. The average power consumption is 262 mW at code rate 4/5 and 200 MHz. The VLSI result shows that our decoder is both memory efficient and area efficient.