A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA
A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA
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DOI：
10.1109/tns.2017.2746626
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发表时间：
2017-10-01
影响因子：
1.8
通讯作者：
Cao, Qiang
中科院分区：
文献类型：
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作者：
Wang, Yonggang;Kuang, Jie;Cao, Qiang
在Xilinx Kintex-7现场可编程门阵列（FPGA）中实现了一个时间间隔均方根精度为3.9 ps、测量吞吐量为277 M事件/秒的时间-数字转换器（TDC）。与以前的工作不同，TDC是用多链抽头延迟线（TDL），其次是一个计数器编码器。将四个常规TDLs合并在一起使得TDC仓非常小，从而可以显著提高时间精度。一计数器编码器自然地将全局气泡误差校正应用于TDL的输出，因此即使当使用利用当前先进工艺技术制造的FPGA时，TDC设计也相对简单。TDC实现是一种普遍适用的方法，可以同时实现高时间精度和高测量吞吐量。
A 3.9-ps time-interval rms precision and 277-M events/second measurement throughput time-to-digital converter (TDC) is implemented in a Xilinx Kintex-7 field programmable gate array (FPGA). Unlike previous work, the TDC is achieved with a multichain tapped-delay line (TDL) followed by an ones-counter encoder. The four normal TDLs merged together make the TDC bins very small, so that the time precision can be significantly improved. The ones-counter encoder naturally applies global bubble error correction to the output of TDL, thus the TDC design is relatively simple even when using FPGAs made with current advanced process technology. The TDC implementation is a generally applicable method that can simultaneously achieve high time precision and high measurement throughput.