A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications
复制标题
DOI：
10.1109/jssc.2020.3034241
复制
发表时间：
2021-01-01
影响因子：
5.4
通讯作者：
Li, Quincy
中科院分区：
文献类型：
--
作者：
Chang, Tsung-Yung Jonathan;Chen, Yen-Huei;Li, Quincy
通过使用采用 EUV 和高迁移率沟道 (HMC) 技术的 5 nm HK 金属栅极 FinFET，成功实现了具有写入辅助电路的 135 Mb 0.021 mu m(2) 6 T 高密度 SRAM 位单元。本文提出了金属电容器耦合负位线 (NBL) 和电荷共享较低单元 VDD (CS-LCV) 写入辅助技术来降低 SRAM 最小电源电压。还采用了飞翔位线 (FBL) 架构，将高密度 SRAM 宏位密度提高了 5%。芯片数据表明，NBL 和 LCV 写入辅助技术均可将整体 SRAM 最小电源电压性能在第 95 个百分位处提高 300 mV 以上。
A 135-Mb 0.021-mu m(2) 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage. Flying bitline (FBL) architecture is also implemented to improve the high-density SRAM macro-bit density by 5%. Silicon data show that both NBL and LCV write-assist techniques can improve the overall SRAM minimal supply voltage performance by more than 300 mV at the 95th percentile.