Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
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缓存架构和接口对基于 FPGA 的处理器/并行加速器系统的性能和面积的影响
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
Tomasz S. Czajkowski
中科院分区：
文献类型：
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作者：
Jongsok Choi;Kevin Nam;Andrew Canis;J. Anderson;S. Brown;Tomasz S. Czajkowski
我们描述了适用于基于fpga的处理器/并行加速器系统的新多端口缓存设计，并评估了它们对应用性能和面积的影响。基线系统包括一个MIPS软处理器和具有共享内存架构的定制硬件加速器：fpga上L1缓存由片外DDR2 SDRAM支持。在这个一般的系统模型中，我们评估了传统的缓存设计参数（缓存大小，行大小，关联性）。在并行加速器上下文中，我们检查缓存设计及其接口的影响。具体来说，我们将研究当多个硬件加速器并行操作（和访问内存）时，缓存端口的数量如何影响性能，并使用以下两种不同的多端口缓存硬件实现进行评估：1)多泵送，以及2)最近发布的基于活值表概念的方法。结果表明，应用程序性能在很大程度上取决于缓存接口和体系结构：对于具有6个加速器的系统，根据缓存设计，相对于基线顺序系统（具有单个加速器和直接映射的2KB缓存，32B行），平均速度波动从0.73 x到6.14 x。考虑到性能和面积，最好的架构是4端口多泵直接映射缓存，缓存大小为16KB，线路大小为128B。
We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. The baseline system comprises a MIPS soft processor and custom hardware accelerators with a shared memory architecture: on-FPGA L1 cache backed by off-chip DDR2 SDRAM. Within this general system model, we evaluate traditional cache design parameters (cache size, line size, associativity). In the parallel accelerator context, we examine the impact of the cache design and its interface. Specifically, we look at how the number of cache ports affects performance when multiple hardware accelerators operate (and access memory) in parallel, and evaluate two different hardware implementations of multi-ported caches using: 1) multi-pumping, and 2) a recently-published approach based on the concept of a live-value table. Results show that application performance depends strongly on the cache interface and architecture: for a system with 6 accelerators, depending on the cache design, speed up swings from 0.73× to 6.14×, on average, relative to a baseline sequential system (with a single accelerator and a direct-mapped, 2KB cache with 32B lines). Considering both performance and area, the best architecture is found to be a 4-port multi-pump direct-mapped cache with a 16KB cache size and a 128B line size.