A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique
A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique
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使用频率整形技术的 50 μW/Ch 伪影不敏感神经记录仪
DOI：
10.1109/cicc.2013.6658532
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
Zhi Yang
中科院分区：
文献类型：
--
作者：
Jian Xu;Zhi Yang
提出了一种频率整形(FS)神经记录接口，该接口可以固有地抑制电极偏移，输入阻抗增加5-10倍，扩展系统动态范围(DR)4.5bit，并对运动伪影和50/60 Hz电源噪声干扰提供更大的容忍度。它被认为更适合长期的脑-机-接口(BMI)实验。为了达到上述性能，该结构采用了自动调零校正以避免系统饱和，采用延迟信令噪声消除来抑制KT/C噪声，并采用自动数据分割技术来降低低频输入参考噪声。在40 kHz采样时钟和±0.6V电源下测量，该记录器的功耗为50μW/ch，其中包括用于FS放大器的22μW、用于增益级放大器的12μW、用于缓冲器的12μW和用于逐次逼近寄存器模数转换器的4μW。所设计的合成孔径雷达模数转换器在160 kHz的带宽内实现了11位的有效比特数。此外，由于采用了FS技术，记录仪具有3pF输入电容和15.5位(11位+4.5位)系统DR。在0.13μm工艺下，所设计的芯片面积为0.76mm2/ch。
This paper presents a frequency-shaping (FS) neural recording interface that can inherently reject electrode offset, 5-10 times increase input impedance, 4.5-bit extend system dynamic range (DR), and provide much more tolerance to motion artifacts and 50/60 Hz power noise interferences. It is supposed to be more suitable for long-term brain-machine-interface (BMI) experiments. To achieve the mentioned performance above, the proposed architecture adopts an auto-zero offset calibration to avoid system saturation, a delayed-signaling noise cancellation to attenuate kT/C noise, and an automatical data-splitting technique to reduce input-referred noise at low frequencies. Measured at a 40 kHz sampling clock and ± 0.6 V supply, the recorder consumes 50 μW/ch, including 22 μW for FS amplifier, 12 μW for gain-stage amplifier, 12 μW for buffer, and 4 μW for successive approximation register (SAR) analog-to-digital converter (ADC). The designed SAR ADC achieves an effective-number-of-bit (ENOB) of 11-bit in a 160 kHz bandwidth. In addition, the recorder has a 3 pF input capacitance and 15.5-bit (11-bit+4.5-bit) system DR due to the utilization of FS technique. The designed chip occupies 0.76 mm2/ch in a 0.13 μm CMOS process.