TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks
TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks
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TD-SRAM：用于二元神经网络的基于时域的内存计算宏
DOI：
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发表时间：
2021
期刊：
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通讯作者：
Ru Huang
中科院分区：
文献类型：
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作者：
Jiahao Song;Yuan Wang;Minguang Guo;Xiang Ji;Kaili Cheng;Yixuan Hu;Xiyuan Tang;Runsheng Wang;Ru Huang
内存计算（IMC）利用了内存中的模拟乘法累加（MAC），有望缓解Von-Neumann瓶颈并提高深度神经网络（DNN）的能量效率。由于时域（TD）计算也是一种节能的模拟计算模式，我们提出了一个8 kb的混合信号IMC宏，TD-SRAM，结合IMC和TD计算。提出了一种双边缘单输入（DESI）TD计算拓扑结构，该拓扑结构可以显著提高TD小区的面积和功率效率。由基于6 T DESI的TD单元和6 T-SRAM单元组成的TD-SRAM位单元支持二进制DNN。在IMC模式下，60列并行工作，每列处理96个输入的二进制MAC操作。TD-SRAM采用标准40 nm CMOS工艺实现，在0.9 V电源电压下实现了537 TOPS/W的高能效。在不同的DNN拓扑结构下，测试芯片在MNIST数据集中使用双2位时间数字转换器（TDC）实现了95.90%-98.00%的精度。
In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%–98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset.