CMOS Integrated Stress Mapping Chips with 32 N-Type or P-Type Piezoresistive Field Effect Transistors
CMOS Integrated Stress Mapping Chips with 32 N-Type or P-Type Piezoresistive Field Effect Transistors
复制标题
具有 32 个 N 型或 P 型压阻场效应晶体管的 CMOS 集成应力映射芯片
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
O. Paul
中科院分区：
文献类型：
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作者：
P. Gieschke;Y. Nurcahyo;M. Herrmann;M. Kuhl;P. Ruther;O. Paul
本文报道了一种新一代的CMOS应力映射芯片，包括32个方形场效应晶体管（FET）与四个源极/漏极接触（piezo-FET），利用剪切压阻效应在n型（NMOS）或p型（PMOS）反型层。芯片总面积为2.5 × 2 mm 2，集成了模拟电路和数字逻辑。当暴露于均匀剪切或正应力时，所有32个集成应力传感器均显示出与理论预测非常一致的线性响应，并具有相同的应力灵敏度。作为单独的器件制造的压电FET的特征在于相对于应力灵敏度，固有偏移和噪声行为。通过在压电场效应晶体管中引入中心孔来提高应力灵敏度。NMOS和PMOS器件的灵敏度分别为-448 <$V/（V MPa）和477 <$V/（V MPa）。
This paper reports a novel generation of CMOS stress mapping chips comprising 32 square field effect transistors (FET) with four source/drain contacts (piezo-FETs) exploiting the shear piezoresistive effect in n-type (NMOS) or p-type (PMOS) inversion layers. The sensor chips with a total die area of 2.5 × 2 mm2 are integrated with analog circuitry and digital logic. When exposed to homogenous shear or normal stress, all 32 integrated stress sensors show a linear response in excellent agreement with theoretical predictions and exhibit identical stress sensitivities. Piezo-FETs fabricated as separate devices are characterized with respect to stress sensitivity, intrinsic offset, and noise behavior. Stress sensitivities are enhanced by incorporating a central hole into the piezo-FETs. Sensitivities of -448 ¿V/(V MPa) and 477 ¿V/(V MPa) were measured for NMOS and PMOS devices, respectively.