FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging
复制标题
用于实时非视距成像的 FPGA 加速器
DOI：
10.1109/tcsi.2021.3122309
复制
发表时间：
2021-11-01
影响因子：
5.1
通讯作者：
Lou, Xin
中科院分区：
文献类型：
--
作者：
Liao, Zhengpeng;Jiang, Deyang;Lou, Xin
Non-line-of-sight (NLOS) imaging systems reconstruct hidden scenes using computational methods based on indirect light that diffusely reflected from relay walls. Due to the computation and memory requirements of reconstruction algorithms, real-time NLOS imaging for room-size scenes based on non-confocal data has long been challenging. This paper proposes a field programmable gate array (FPGA) accelerator for the recently proposed Rayleigh-Sommerfeld Diffraction (RSD)-based NLOS reconstruction method. In the proposed accelerator design, ring sampling and radius sampling techniques are proposed to reduce the memory requirements by reconstructing the RSD kernels with a set of kernel bases and ring sampling coefficients during the runtime. Based on that, a customized hardware architecture and the corresponding FPGA design for real-time RSD-based NLOS reconstruction is further proposed. Implementation results show that the proposed FPGA accelerator is capable of reconstructing NLOS scenes at 25 frames per second (FPS), running at a relatively slow clock frequency of 50 MHz. To the best knowledge of the authors, this is the first real-time enabled FPGA accelerator for room-size NLOS imaging with a resolution of $128\times 128$ .
