Impact of Technology Scaling on SRAM Soft Error Rates
Impact of Technology Scaling on SRAM Soft Error Rates
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DOI：
10.1109/tns.2014.2365546
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发表时间：
2014-11
影响因子：
1.8
通讯作者：
I. Chatterjee;B. Narasimham;N. Mahatme;B. Bhuva;R. Reed;peixiong zhao;J. K. Wang;N. Vedula;B. Bartz;C. Monzel
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文献类型：
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作者：
I. Chatterjee;B. Narasimham;N. Mahatme;B. Bhuva;R. Reed;peixiong zhao;J. K. Wang;N. Vedula;B. Bartz;C. Monzel
在过去几代技术中，三阱和双阱 SRAM 电路的软错误率表现出明显不一致的行为。这项工作比较了各种粒子 LET 中 28、40 和 65 nm 双阱和三阱 SRAM 中的重离子引起的翻转横截面。对所有这些技术的相同布局进行类似实验以及 3D TCAD 模拟，用于确定单事件扰乱的主要机制。结果表明，良好的设计对 SRAM 的单事件响应有很大影响。布局也起着重要作用，精心设计和布局的综合效果决定了先进技术节点中制造的 SRAM 的软错误敏感性。
Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.