Design Considerations for Complementary Nanoelectromechanical Logic Gates

Design Considerations for Complementary Nanoelectromechanical Logic Gates
复制标题

DOI：
10.1109/iedm.2007.4418930
复制
发表时间：
2007-12
期刊：
2007 IEEE International Electron Devices Meeting
影响因子：
--
通讯作者：
K. Akarvardar;D. Elata;R. Parsa;G. Wan;K. Yoo;J. Provine;P. Peumans;R. Howe;H. Wong
K. Akarvardar;D. Elata;R. Parsa;G. Wan;K. Yoo;J. Provine;P. Peumans;R. Howe;H. Wong
中科院分区：
其他
文献类型：
--
作者：
K. Akarvardar;D. Elata;R. Parsa;G. Wan;K. Yoo;J. Provine;P. Peumans;R. Howe;H. Wong

文献摘要

被引文献

相似文献

研究了互补纳米机电(CNEM)逻辑门的工作原理和性能。考虑了尺寸比目前的MEMS继电器小2到3个数量级的NEMS结构。各种金属以硅为基准作为悬臂梁材料。结果表明，采用横向激励光束、10 nm间隙和低密度材料(如Si或Al)的CNEM逆变器在VDD=1.5V时可以获得纳秒延迟和小于0.1fJ的开关能量，而面积仅为0.03微米2。
The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at VDD = 1.5 V while occupying an area as small as 0.03 mum2.