Synthesis of Parallel Synchronous Software
Synthesis of Parallel Synchronous Software
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DOI：
10.1109/les.2020.2992051
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发表时间：
2020-05
影响因子：
1.6
通讯作者：
Pantea Kiaei;P. Schaumont
中科院分区：
文献类型：
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作者：
Pantea Kiaei;P. Schaumont
在典型的嵌入式应用程序中，该程序的精确执行时间无关紧要，足以满足实时截止日期。但是，由于定时侧通道泄漏的风险，现代信息安全性的应用已变得更加敏感。此类程序的时机需要与数据无关和精确。我们描述了一个并行同步软件模型，该模型在带有单词长度$ n $的处理器上执行为$ n $并行线程。每个线程都是单位同步机，具有精确，无争议的时间，而$ n $螺纹中的每个线程仍以独立的计算机执行。最终的软件支持细粒的并行执行。与早期的工作以获取软件中的精确和可重复的时机相反，我们的解决方案不需要对处理器体系结构或专门的指令计划技术进行修改。此外，所有线程都并联并且没有争议，从而消除了线程调度的问题。我们使用硬件（HDL）语义将线程描述为单位同步机。使用逻辑合成和代码生成，我们得出了此设计的并行同步实现。我们说明了同步并行编程模型，其中包含来自密码学和其他具有精确时序要求的应用程序的实例。
In typical embedded applications, the precise execution time of the program does not matter and it is sufficient to meet a real-time deadline. However, modern applications in information security have become much more time-sensitive due to the risk of timing side-channel leakage. The timing of such programs needs to be data-independent and precise. We describe a parallel synchronous software model, which executes as $N$ parallel threads on a processor with word-length $N$ . Each thread is a single-bit synchronous machine with precise, contention-free timing, while each of the $N$ threads still executes as an independent machine. The resulting software supports fine-grained parallel execution. In contrast to earlier work to obtain precise and repeatable timing in software, our solution does not require modifications to the processor architecture nor specialized instruction scheduling techniques. In addition, all threads run in parallel and without contention, which eliminates the problem of thread scheduling. We use hardware (HDL) semantics to describe a thread as a single-bit synchronous machine. Using logic synthesis and code generation, we derive a parallel synchronous implementation of this design. We illustrate the synchronous parallel programming model with practical examples from cryptography and other applications with precise timing requirements.