Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges
Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges
复制标题
基于 ARM926 SoC 的低功耗 MTCMOS 案例研究：设计、分析和测试挑战
DOI：
10.1109/test.2007.4437661
复制
发表时间：
2007
期刊：
影响因子：
--
通讯作者：
Sachin Idgunji
中科院分区：
文献类型：
--
作者：
Sachin Idgunji
诸如多电压岛、电压缩放和功率门控的低功率技术正在获得发展，以解决在运行时间期间以及在待机模式期间管理能量和功率的需求。这些设计技术增加了实现和分析电源网络的复杂性，以满足所需的平均IR下降的要求，瞬态导通涌入（涌出）电流以及在runtime.We设计的动态电压降基于ARM926的SoC，实现了上述技术，包括多阈值CMOS（MTCMOS）为基础的处理器内核。为了分析与功率门控相关的效应的影响，作为逻辑设计的一部分，我们内置了一个系统，该系统使用基于扫描链的网络来观察虚拟电源网络上的瞬态电流对状态保持的影响。该系统还可用于在使用MTCMOS网络关闭设计时检查保持锁存器的完整性。
Low power techniques such as multi-voltage islands, voltage scaling and power gating are gaining ground to address the need for managing energy and power during run time as well as during standby modes. These design techniques increase the complexity of implementing and analyzing the power network to meet the required average IR drop requirements , transient turn on in-rush (out-rush) currents as well as dynamic voltage drops during runtime.We designed an ARM926 based SoC that implements the above techniques including a multi-threshold CMOS (MTCMOS) based processor core. To analyze the effects of effects associated with power gating we have built in, as part of the logic design , a system that uses the scan chain based network to observe the effects of transient currents on the virtual power network on state retention . The system can also be used to check the integrity of the retention latches when the design has been powered off using the MTCMOS network.