Test-set reordering for improving diagnosability
Test-set reordering for improving diagnosability
复制标题
测试集重新排序以提高可诊断性
DOI：
10.1109/vts.2017.7928926
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
R. D. Blanton
中科院分区：
文献类型：
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作者：
Cheng Xue;R. D. Blanton
集成电路的精确逻辑诊断能够快速分析缺陷位置及其相应行为，从而获得有价值的反馈，从而实现快速良率提升。然而，在大批量生产过程中，有限的测试仪时间或内存限制了每个故障芯片可以记录的数据量，从而使诊断变得更加困难。为了帮助缓解这一挑战，开发了一种测试重新排序方法，以提高未能通过基于扫描的逻辑测试的芯片的可诊断性。实验结果表明，使用本工作中描述的方法重新排序测试后，两个工业设计的具有完美诊断分辨率的故障芯片数量分别增加了 10.6% 和 5.1%。
Precise and accurate logic diagnosis for integrated circuits enables fast analysis of defect locations and their corresponding behaviors that leads to valuable feedback for achieving fast yield ramp-up. However during large-volume production, limited tester time or memory restrict the amount of data that can be recorded for each failing chip, thus making diagnosis more difficult. To help mitigate this challenge, a test-reordering method is developed to improve diagnosability for chips that fail scan-based logic testing. Experiment results show that the number of failing chips with perfect diagnostic resolution is increased by 10.6% and 5.1%, respectively, for two industrial designs after tests are reordered using the method described in this work.