Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks
Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks
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DOI：
10.1109/dac18074.2021.9586242
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发表时间：
2021-12
期刊：
影响因子：
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通讯作者：
Gaurav Kolhe;Soheil Salehi;T. Sheaves;H. Homayoun;S. Rafatirad;Sai Manoj Pudukotai Dinakarrao;Avesta Sasan
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文献类型：
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作者：
Gaurav Kolhe;Soheil Salehi;T. Sheaves;H. Homayoun;S. Rafatirad;Sai Manoj Pudukotai Dinakarrao;Avesta Sasan
在技术先进的硅行业中，利润最大化同时风险最小化推动了制造工艺和电子硬件供应链的全球化。然而，随着成功硬件攻击的规模不断增加，许多硬件IP的安全性已经受到损害。许多现有的安全工作都专注于解决单个漏洞，而忽略了其他威胁。为此，我们提出了一种新颖的方法，利用新兴的基于自旋的设备，通过逻辑混淆，在制造过程和供应链中保护硬件 IP。我们提出的动态混淆方法使用可重新配置的逻辑和互连块（RIL-Blocks），由基于磁随机存取存储器（MRAM）的查找表和开关盒组成，具有针对最先进的基于 SAT 的攻击和功率侧信道攻击的灵活性和弹性，同时产生少量开销。拟议的扫描启用混淆电路混淆了预言机电路的响应，并进一步强化了 RIL 块提供的逻辑和路由混淆，类似于深度防御方法。对 ISCAS 基准和通用评估平台 (CEP) 电路上提议的 RIL-Block 提供的安全性的实证评估表明，弹性会降低开销，同时为各种硬件安全威胁提供弹性。
Maximizing profits while minimizing risk in a technologically advanced silicon industry has motivated the globalization of the fabrication process and electronic hardware supply chain. However, with the increasing magnitude of successful hardware attacks, the security of many hardware IPs has been compromised. Many existing security works have focused on resolving a single vulnerability while neglecting other threats. This motivated to propose a novel approach for securing hardware IPs during the fabrication process and supply chain via logic obfuscation by utilizing emerging spin-based devices. Our proposed dynamic obfuscation approach uses reconfigurable logic and interconnects blocks (RIL-Blocks), consisting of Magnetic Random Access Memory (MRAM)-based Look Up Tables and switch boxes flexibility and resiliency against state-of-the-art SAT-based attacks and power side-channel attacks while incurring a small overhead. The proposed Scan Enabled Obfuscation circuitry obfuscates the oracle circuit’s responses and further fortifies the logic and routing obfuscation provided by the RIL-Blocks, resembling a defense-in-depth approach. The empirical evaluation of security provided by the proposed RIL-Blocks on the ISCAS benchmark and common evaluation platform (CEP) circuit shows that resiliency comes with reduced overhead while providing resiliency to various hardware security threats.