Leveraging hardware TM in Haskell
Leveraging hardware TM in Haskell
复制标题
在 Haskell 中利用硬件 TM
DOI:
10.1145/3293883.3295711
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发表时间:
2019
期刊:
影响因子:
--
通讯作者:
Scott, Michael L.
中科院分区:
文献类型:
--
作者:
Yates, Ryan;Scott, Michael L.
Transactional memory (TM) is heavily used for synchronization in the Haskell programming language, but its performance has historically been poor. We set out to improve this performance using hardware TM (HTM) on Intel processors. This task is complicated by Haskell's retry mechanism, which requires information to escape aborted transactions, and by the heavy use of indirection in the Haskell runtime, which means that even small transactions are likely to over-flow hardware buffers. It is eased by functional semantics, which preclude irreversible operations; by the static separation of transactional state, which precludes privatization; and by the error containment of strong typing, which enables so-calledlazy subscriptionto the lock that protects the "fallback" code path.We describe a three-level hybrid TM system for the Glasgow Haskell Compiler (GHC). Our system first attempts to perform an entire transaction in hardware. Failing that, it falls back to software tracking of read and write sets combined with a commit-time hardware transaction. If necessary, it employs a global lock to serialize commits (but still not the bodies of transactions). To get good performance from hardware TM while preserving Haskell semantics, we use Bloom filters for read and write set tracking. We also implemented and extended the newly proposedmutable constructor fieldslanguage feature to significantly reduce indirection. Experimental results with complex data structures show significant improvements in throughput and scalability.
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DOI:
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发表时间:
1998
期刊:
JACM
影响因子:
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作者:
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2008
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International Conference on Parallel Processing
影响因子:
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影响因子:
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2014
期刊:
arXiv.org
影响因子:
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2001
期刊:
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作者:
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通讯作者:
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