Parallel Error Detection Using Heterogeneous Cores
Parallel Error Detection Using Heterogeneous Cores
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DOI：
10.1109/dsn.2018.00044
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发表时间：
2018-06
期刊：
影响因子：
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通讯作者：
S. Ainsworth;Timothy M. Jones
中科院分区：
文献类型：
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作者：
S. Ainsworth;Timothy M. Jones
微处理器错误检测越来越重要，因为现代系统中晶体管的数量增加了它们的脆弱性。此外，由于严格的安全标准，汽车和保健行业等领域的许多现代工作量越来越不耐受。但是，当前的检测技术需要复制所有硬件结构，从而导致功耗和芯片面积大幅增加。文献中的解决方案涉及在同一硬件上多次运行代码，这大大降低了性能，无法捕获所有错误。我们设计了一种新颖的硬件解决方案以进行错误检测，该解决方案利用了原始执行中可能不存在的检查代码中的并行性。我们将高性能的外部核心与一组小的低功率内核配对，每个内核都检查了一部分排序核心的执行。我们的系统可以检测到硬错误和软误差，区域低，功率和性能开销。
Microprocessor error detection is increasingly important, as the number of transistors in modern systems heightens their vulnerability. In addition, many modern workloads in domains such as the automotive and health industries are increasingly error intolerant, due to strict safety standards. However, current detection techniques require duplication of all hardware structures, causing a considerable increase in power consumption and chip area. Solutions in the literature involve running the code multiple times on the same hardware, which reduces performance significantly and cannot capture all errors. We have designed a novel hardware-only solution for error detection, that exploits parallelism in checking code which may not exist in the original execution. We pair a high-performance out-of-order core with a set of small low-power cores, each of which checks a portion of the out-of-order core's execution. Our system enables the detection of both hard and soft errors, with low area, power and performance overheads.