Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology
Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology
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DOI：
10.1109/dcis.2018.8681497
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发表时间：
2018-11
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影响因子：
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通讯作者：
Kexin Yang;Rui Zhang;Taizhi Liu;Dae-Hyun Kim;L. Milor
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作者：
Kexin Yang;Rui Zhang;Taizhi Liu;Dae-Hyun Kim;L. Milor
本文提出了一种方法，以找到最佳的加速测试区域的寿命参数估计不仅是传统的可靠性问题，前端的线介质击穿（FEOL TDDB），但也是新兴的磨损机制，中间的线时间相关的介质击穿（MOL TDDB）在14纳米FinFET技术。介绍了寻找最优测试区域的框架，详细讨论了误差估计方法。三个数字电路的评估和比较。最佳测试区域取决于电路的大小以及电路中标准单元的类型。为保证寿命参数的准确估计，应同时考虑采样误差和选择性误差。作为一般指导原则，通过在较高电压下测试栅极TDDB寿命参数，同时在较高温度下测试中间线TDDB，将实现更高的估计精度。
This paper proposes a methodology to find optimal accelerated test regions for lifetime parameter estimation for not only the traditional reliability concern, frontend-of-line dielectric breakdown (FEOL TDDB), but also the newly emerging wearout mechanism, middle-of-line time dependent dielectric breakdown (MOL TDDB) in 14nm FinFET technology. The framework to find the optimal test regions is introduced; the error estimating methodology is discussed in detail. Three digital circuits are presented for evaluation and comparison. The optimal test regions depend on the circuit size as well as the types of standard cells in the circuits. To ensure accurate lifetime parameter estimation, both error from sampling and error from selectivity should be considered at the same time. As a general guideline, higher estimation accuracy will be achieved by testing gate TDDB lifetime parameters at higher voltages, while testing middle-of-line TDDB at higher temperatures.