GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs
GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs
复制标题
GliFreD：在 FPGA 上实现功率均衡电路的无干扰复制
DOI：
10.1109/tc.2017.2651829
复制
发表时间：
2018
影响因子：
3.7
通讯作者：
Tim Güneysu
中科院分区：
文献类型：
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作者：
A. Wild;A. Moradi;Tim Güneysu
安全硬件的设计人员需要加强其实现以抵御物理威胁，例如电源分析攻击。特别地，密码硬件电路需要将其电流消耗与通过处理（秘密）数据推断的信息解相关。实现这一目标的常用技术是使用特殊的逻辑风格，旨在均衡每个处理步骤的电流消耗。然而，由于所有隐藏技术（如双轨预充电（DRP））最初都是为ASIC开发的，因此在具有固定和预定义逻辑结构的FPGA器件上部署此类对策构成了特殊的挑战。在这项工作中，我们提出了一个新的DRP计划（GliFreD），专门为FPGA平台设计，并进行了实际评估。GliFreD克服了众所周知的早期传播问题，防止毛刺，使用隔离的双轨概念，并减轻不平衡的路由。通过所有这些功能，GliFreD大大超过了以前报道的任何FPGA相关对策所达到的物理安全水平。
Designers of secure hardware are required to harden their implementations against physical threats, such as power analysis attacks. In particular, cryptographic hardware circuits need to decorrelate their current consumption from the information inferred by processing (secret) data. A common technique to achieve this goal is the use of special logic styles that aim at equalizing the current consumption at each single processing step. However, since all hiding techniques like Dual-Rail Precharge (DRP) were originally developed for ASICs, the deployment of such countermeasures on FPGA devices with fixed and predefined logic structure poses a particular challenge. In this work, we propose and practically evaluate a new DRP scheme (GliFreD) that has been exclusively designed for FPGA platforms. GliFreD overcomes the well-known early propagation issue, prevents glitches, uses an isolated dual-rail concept, and mitigates imbalanced routings. With all these features, GliFreD significantly exceeds the level of physical security achieved by any previously reported, related countermeasures for FPGAs.