A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization
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基于变化感知泰勒展开图的 Nano-CMOS 寄存器传输级泄漏优化方法
DOI：
10.1166/jolpe.2011.1160
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发表时间：
2011
影响因子：
--
通讯作者：
Banerjee S
中科院分区：
文献类型：
--
作者：
Banerjee S
随着CMOS工艺向纳米级发展，工艺参数的变化对电路特性有着深远的影响。在纳米CMOS电路设计中的这种工艺变化下满足时序和功率约束正变得越来越困难。在电路抽象的每一个层次上，已经发生了从基于最坏情况的分析和优化到基于统计或概率的分析和优化的转变。本文提出了一种基于泰勒展开图（TED）的高级综合（HLS）统计优化方法。提出了一种可变感知的同时调度和资源绑定算法，该算法在定时收益和性能约束下最大化功率收益。为了这个目的，在45 nm CMOS的多氧化物厚度（多Tox）库的特征在于根据工艺变化。准确分析了不同功能单元的延迟和功率分配。所提出的变化感知算法使用这些组件生成低功耗寄存器传输级（RTL）的描述下，给定的时序产量和性能约束。实验结果表明，在给定的约束条件下，泄漏功率产额显着提高高达95%。
As the CMOS technology scales down to nanometer regime the process variations have profound effect on circuit attributes. Meeting timing and power constraints under such process variations in nano-CMOS circuit design is becoming increasingly difficult. A shifting from worst-case based analysis and optimization to statistical or probability based analysis and optimization at every level of circuit abstraction has happened. This paper presents a Taylor Expansion Diagram (TED) based approach for statistical optimization during high-level synthesis (HLS). A variation-aware simultaneous scheduling and resource binding algorithm is proposed which maximizes the power yield under timing yield and performance constraint. For this purpose, a multiple-oxide thickness (multi-Tox ) library at 45 nm CMOS is characterized under process variation. The delay and power distribution of different functional units are accurately analyzed. The proposed variation-aware algorithm uses those components for generating low-power register-transfer level (RTL) descriptions under a given timing yield and performance constraint. The experimental results show significant improvement as high as 95% on leakage power yield under given constraints.