Use of Particle Swarm Optimization to Design Combinational Logic Circuits
Use of Particle Swarm Optimization to Design Combinational Logic Circuits
复制标题
DOI：
10.1007/3-540-36553-2_36
复制
发表时间：
2003-03
期刊：
影响因子：
--
通讯作者：
C. C. Coello-C.;Erika Hernández Luna;A. H. Aguirre
中科院分区：
文献类型：
--
作者：
C. C. Coello-C.;Erika Hernández Luna;A. H. Aguirre
本文提出了一种基于二进制粒子群优化的门级组合逻辑电路设计方案。使用文献中的几个示例对所提出的算法进行了验证，并与遗传算法（具有整数表示）以及使用传统电路设计辅助工具（例如卡诺图）的人类设计人员进行了比较。结果表明，粒子群优化可能是门级组合电路设计的可行替代方案。
This paper presents a proposal based on binary particle swarm optimization to design combinational logic circuits at the gatelevel. The proposed algorithm is validated using several examples from the literature, and is compared against a genetic algorithm (with integer representation), and against human designers who used traditional circuit design aids (e.g., Karnaugh Maps). Results indicate that particle swarm optimization may be a viable alternative to design combinational circuits at the gate-level.