Delivering Performance-Portable Stencil Computations on CPUs and GPUs Using Bricks
Delivering Performance-Portable Stencil Computations on CPUs and GPUs Using Bricks
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使用 Brick 在 CPU 和 GPU 上提供性能可移植的模板计算
DOI：
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发表时间：
2018
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通讯作者：
H. Johansen
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作者：
Tuowen Zhao;Samuel Williams;Mary W. Hall;H. Johansen
实现模板计算的高性能对现代架构提出了许多挑战。优化策略在不同的体系结构、不同类型的支架和不同类型的应用程序之间有很大的差异。编译器和应用程序员使用的使模板计算适应不同架构的标准方法是通过使用迭代空间平铺，由此调整计算的数据占用及其计算分区以匹配不同平台的存储器层次结构和可用并行性。在本文中，我们探讨了一种替代的性能可移植性策略的stenetron，一个数据布局库的stenetron称为砖，适应数据足迹和并行通过细粒度的数据块。砖被设计成利用StenomeTM固有的多维空间局部性，促进可以适应CPU或GPU的改进的代码生成，并减少对存储器系统的压力。我们证明了砖是跨CPU和GPU架构的性能移植，并提供各种平铺策略的性能优势，特别是对于现代多模板和高阶模板计算。对于一系列模板计算，我们在英特尔Knights Landing（Xeon Phi）和Skylake（Xeon）CPU以及NVIDIA P100（Pascal）GPU上实现了高性能，针对平铺代码提供了高达5倍的加速。
Achieving high performance on stencil computations poses a number of challenges on modern architectures. The optimization strategy varies significantly across architectures, types of stencils, and types of applications. The standard approach to adapting stencil computations to different architectures, used by both compilers and application programmers, is through the use of iteration space tiling, whereby the data footprint of the computation and its computation partitioning are adjusted to match the memory hierarchy and available parallelism of different platforms. In this paper, we explore an alternative performance portability strategy for stencils, a data layout library for stencils called bricks, that adapts data footprint and parallelism through fine-grained data blocking. Bricks are designed to exploit the inherent multi-dimensional spatial locality of stencils, facilitating improved code generation that can adapt to CPUs or GPUs, and reducing pressure on the memory system. We demonstrate that bricks are performance-portable across CPU and GPU architectures and afford performance advantages over various tiling strategies, particularly for modern multi-stencil and high-order stencil computations. For a range of stencil computations, we achieve high performance on both the Intel Knights Landing (Xeon Phi) and Skylake (Xeon) CPUs as well as the NVIDIA P100 (Pascal) GPU delivering up to a 5x speedup against tiled code.