A 16–20 GHz LO system with 115 fs jitter for 24–30 GHz 5G in 28 nm FD-SOI CMOS
A 16–20 GHz LO system with 115 fs jitter for 24–30 GHz 5G in 28 nm FD-SOI CMOS
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采用 28 nm FD-SOI CMOS 的 16–20 GHz LO 系统，适用于 24–30 GHz 5G，具有 115 fs 抖动
DOI：
10.1109/esscirc.2017.8094573
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
H. Sjöland
中科院分区：
文献类型：
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作者：
Staffan Ek;Tony Påhlsson;A. Carlsson;A. Axholt;A. Stenman;H. Sjöland
提出了一种针对5G的毫米波LO信号生成系统。所提出的概念实现了高LO频谱纯度在毫米波频率使用标准CMOS SOI技术。测量的性能符合5G室外系统要求，由于多径传播，5G室外系统需要比最近的室内mmW系统（如IEEE 802.11ad）更小的子载波间隔。一组两个分数N，PLL为基础的频率合成器的可扩展LO系统的建议已实现在28 nm FD-SOI CMOS工艺，其中一个实例的芯片面积仅为0.11 mm 2。对于28 GHz载波，每个PLL的带内相位噪声均低于−100 dBc/Hz，而1.2 V电源功耗仅为15 mW。FoMj为−244 dB，这是该频率范围内小数N分频PLL的最佳报告值。
A system for mmW LO signal generation targeting 5G is presented. The proposed concept achieves high LO spectral purity at mmW frequencies using standard CMOS SOI technology. The measured performance is in line with 5G outdoor system requirements, which due to multi-path propagation require a smaller sub-carrier spacing than recent indoor mmW systems like IEEE 802.11ad. A set of two fractional-N, PLL based frequency synthesizer instances of the scalable LO system proposed has been implemented in 28 nm FD-SOI CMOS technology, where the chip area of one instance is only 0.11 mm2. Each PLL achieves an in-band phase noise below −100 dBc/Hz for a 28 GHz carrier while consuming just 15 mW from a 1.2 V supply. The FoMj is −244 dB which is the best reported figure for a fractional-N PLL in this frequency range.