Configurable isolation: building high availability systems with commodity multi-core processors
Configurable isolation: building high availability systems with commodity multi-core processors
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DOI：
10.1145/1250662.1250720
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发表时间：
2007-06
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通讯作者：
Nidhi Aggarwal;Parthasarathy Ranganathan;N. Jouppi;James E. Smith
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作者：
Nidhi Aggarwal;Parthasarathy Ranganathan;N. Jouppi;James E. Smith
高可用性是企业系统日益重要的需求，通常比性能更有价值。为高可用性而设计的系统通常使用冗余硬件进行错误检测，并在发生故障时保持正常运行时间。具有大量相同资源（如内核、缓存和互连网络）的芯片多处理器似乎是在芯片上实现高可用性解决方案的理想构建块。然而，这样做在错误控制和故障组件替换方面带来了重大挑战。随着未来技术规模的扩大，硅和瞬态故障率的增加会加剧这一问题。本文为未来多核处理器构建的高可用性系统提出了一种新颖、经济的体系结构。我们提出了一种新的芯片多处理器架构，该架构基于对商品设计的经济有效的修改，为故障遏制和组件退役提供可配置的隔离。该设计针对最先进的工业故障模型进行了评估，结果表明，即使在故障率很高的情况下，所提出的架构也能提供有效的故障隔离和优雅的降级。
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redundant hardware for error detection and continued uptime in the event of a failure. Chip multiprocessors with an abundance of identical resources like cores, cache and interconnection networks would appear to be ideal building blocks for implementing high availability solutions on chip. However, doing so poses significant challenges with respect to error containment and faulty component replacement. Increasing silicon and transient fault rates with future technology scaling exacerbate the problem. This paper proposes a novel, cost-effective, architecture for high availability systems built from future multi-core processors. We propose a new chip multiprocessor architecture that provides configurable isolation for fault containment and component retirement, based upon cost-effective modifications to commodity designs. The design is evaluated for a state-of-the-art industrial fault model and the proposed architecture is shown to provide effective fault isolation and graceful degradation even when the failure rate is high.