On-chip multi-GHz clocking with transmission lines
On-chip multi-GHz clocking with transmission lines
复制标题
带传输线的片上多 GHz 时钟
DOI：
10.1109/isscc.2000.839818
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
M. Yamashina
中科院分区：
文献类型：
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作者：
M. Mizuno;K. Anjo;H. Wakabayashi;T. Mogami;T. Horiuchi;M. Yamashina
在高速lsi的生产中，当时钟频率增加到1千兆赫兹以上时，时钟成为性能限制因素。减少时钟偏差的主要障碍是：(1)时钟偏差对器件参数、电源电压和温度变化的敏感性；(2)电感效应，在网格或鱼骨时钟网络等网络中，为了更快地传输信号，需要降低电阻，这使得电感效应变得复杂；(3)功耗。利用电感效应和使用100mm /sup 2/ 5ghz时钟网络克服了这些障碍。该网络值得注意的是：(1)由于时钟树/网格结构考虑了光速，时钟偏差为20ps / pp；(2)由于多层和图图化地平面微带结构，特性阻抗具有可控性；(3)由于使用阻抗控制传输线效应，对工艺和电源变化具有高抗扰性；(4)由于反射波回收，功耗降低66%。
In the production of high-speed LSIs, clocking becomes a performance limiter when the clock frequency increases to one gigahertz and beyond. The major obstacles to the reduction of clock-skew are: (1) clock-skew sensitivity to variations in device parameters, supply voltages, and temperatures, (2) inductive effects, which are complicated by the resistance reduction needed for faster signal transmission in such networks as grid or fish-bone clocking networks and (3) power consumption. Taking advantage of the effect of inductance and using a 100 mm/sup 2/ 5 GHz clocking network overcomes these obstacles. The network is notable for (1) 20 ps pp clock skew due to a clock tree/grid structure that takes light speed into consideration, (2) controllability of characteristic impedance due to a multilayered and patterned ground plane microstrip structure, (3) high immunity to process and power supply variations due to use of impedance-controlled transmission line effects, and (4) 66% power reduction due to reflected wave recycling.