Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
复制标题
使用阈值逻辑触发器降低标准单元 ASIC 的功耗、漏电和面积
DOI：
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发表时间：
2016
影响因子：
2.8
通讯作者：
S. Vrudhula
中科院分区：
文献类型：
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作者：
Niranjan S. Kulkarni;Jinghua Yang;Jae;S. Vrudhula
在本文中，我们描述了一种新的方法，以减少动态功耗，泄漏，和面积的专用集成电路，而不牺牲性能。该方法是基于阈值逻辑门（TLG）的设计和传统的标准单元设计流程的无缝集成。首先，我们描述了一个新的强大的，标准单元库的可配置电路实现阈值功能。抽象地说，阈值门表现为多输入、单输出、边沿触发的触发器，其在时钟边沿上计算输入的阈值函数。该库由少量单元组成，每个单元可以计算一组复杂的阈值函数，否则需要多级网络。由给定阈值门实现的函数由信号如何映射到其输入来确定。本文提出了一种将信号分配到阈值门的输入端以实现给定阈值函数的方法。接下来，我们提出了一种算法，取代了一个子集的触发器和他们的逻辑锥在传统的逻辑网表的一部分，从图书馆的阈值门。由此产生的电路，与传统和TLG（称为混合电路），放置和路由使用商业工具。我们展示了显着减少（使用postlayout模拟）的功率，泄漏，和面积的混合电路相比，传统的逻辑电路，当两者都在最大可能的频率操作的传统设计。
In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.