New Validation and Test Problems for High Performance Deep Sub-micron VLSI Circuits
New Validation and Test Problems for High Performance Deep Sub-micron VLSI Circuits
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DOI：
10.1109/icvd.2000.812575
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发表时间：
2000-01
期刊：
影响因子：
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通讯作者：
M. Breuer;S. Gupta
中科院分区：
文献类型：
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作者：
M. Breuer;S. Gupta
本教程将侧重于（1）新的验证和测试问题，（2）相关基础电气现象的基本模型和分析，（3）生成验证和测试测试测试的技术，这将考虑到这些问题，以及（4）几个现实案例研究。将讨论的导致验证和测试领域范式转变的主要因素是（1）深亚微米CMOS技术，（2）高性能系统架构，（3）信号的短上升/下降时间，以及（4）由于工艺变化引起的电气参数值的变化。这些因素会影响R、L、C、dI/dt和dV/dt值，进而影响接地反弹和时钟偏移，并导致串扰、过冲和下冲。反过来，这些影响性能。
This tutorial will focus on (1) the new validation and test issues, (2) basic models and analysis of the related underlying electrical phenomena, (3) techniques to generate tests for validation and testing, which would take into account these issues, and (4) several real-life case studies. The primary factors causing a paradigm shift in the area of validation and test that will be discussed are (1) deep submicron CMOS technology, (2) high performance system architecture, (3) short rise/fall times of signals, and (4) variations in electrical parameter values due to process variations. These factors influence R, L, C, dI/dt, and dV/dt values, which in turn impact ground bounce and clock skew and cause crosstalk and overshoots and undershoots. In turn, these impact performance.