Elastic bundles : modelling and architecting asynchronous circuits with granular rigidity
Elastic bundles : modelling and architecting asynchronous circuits with granular rigidity
复制标题
DOI：
--
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Johnson Fernandes
中科院分区：
文献类型：
--
作者：
Johnson Fernandes
如今的集成电路 (IC) 设计主要是片上系统 (SoC)。多年来，由于不断增长的工艺和环境变化以及全球时钟分配的难度，设计 SoC 的复杂性迅速增加。此外，传统的同步设计无法处理现代 SoC 的异构时序特性。作为对策，半导体行业见证了异步设计原理的强劲复兴。结果，出现了一种新的数字电路范式，即混合同步异步电路。随着最近同步异步 CAD 集成的创新浪潮，这种范例在未来的 SoC 中显示出商业采用的迹象，这主要是由于同步功能块和 IP 核的重用范围，以及同步和异步设计风格在通用 EDA 框架中的共存。然而，缺乏正式的方法和工具来促进混合同步异步设计。在本文中，我们提出了一种基于 Petri 网的形式模型，具有步骤语义来描述这些电路的行为。研究了该模型在同步异步混合电路验证和综合中的应用。迄今为止，这种范式主要是在全局异步局部同步（GALS）系统的基础上进行探索的。尽管经过数十年的研究，GALS 设计仍未能在商业上获得关注。为了了解其缺点，我们提出了一个表征 GALS SoC 物理和功能方面的仿真框架。提出了一种合成具有不同刚性水平的混合同步异步电路的新方法。从本质上异步的系统的高级数据流模型开始，关键思想是在模型中引入所选粒度级别的刚性，而不改变功能行为。然后，系统被划分为同步和异步元件的功能块，然后转换为可以使用标准 EDA 工具合成的等效电路。
Integrated Circuit (IC) designs these days are predominantly System-on-Chips (SoCs). The complexity of designing a SoC has increased rapidly over the years due to growing process and environmental variations coupled with global clock distribution di culty. Moreover, traditional synchronous design is not apt to handle the heterogeneous timing nature of modern SoCs. As a countermeasure, the semiconductor industry witnessed a strong revival of asynchronous design principles. A new paradigm of digital circuits emerged, as a result, namely mixed synchronous-asynchronous circuits. With a wave of recent innovations in synchronous-asynchronous CAD integration, this paradigm is showing signs of commercial adoption in future SoCs mainly due to the scope for reuse of synchronous functional blocks and IP cores, and the co-existence of synchronous and asynchronous design styles in a common EDA framework. However, there is a lack of formal methods and tools to facilitate mixed synchronousasynchronous design. In this thesis, we propose a formal model based on Petri nets with step semantics to describe these circuits behaviourally. Implication of this model in the veri cation and synthesis of mixed synchronous-asynchronous circuits is studied. Till date, this paradigm has been mainly explored on the basis of Globally Asynchronous Locally Synchronous (GALS) systems. Despite decades of research, GALS design has failed to gain traction commercially. To understand its drawbacks, a simulation framework characterising the physical and functional aspects of GALS SoCs is presented. A novel method for synthesising mixed synchronous-asynchronous circuits with varying levels of rigidity is proposed. Starting with a high-level data ow model of a system which is intrinsically asynchronous, the key idea is to introduce rigidity of chosen granularity levels in the model without changing functional behaviour. The system is then partitioned into functional blocks of synchronous and asynchronous elements before being transformed into an equivalent circuit which can be synthesised using standard EDA tools.