Design of Hybrid Dual-Path DC-DC Converter with Wide Input Voltage Efficiency Improvement
Design of Hybrid Dual-Path DC-DC Converter with Wide Input Voltage Efficiency Improvement
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具有宽输入电压效率提升的混合双路 DC-DC 转换器设计
DOI：
10.1109/iscas51556.2021.9401442
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
Bo Zhang
中科院分区：
文献类型：
--
作者：
Shaowei Zhen;Yang Rui;Dongming Wu;Yu;Ping Luo;Bo Zhang
提出了一种在宽输入电压范围内提高转换效率的IV型双路降压（T4 DPSD）变换器。提出的T4 DPSD变换器采用电感和飞跨电容作为功率转换元件，减少了传统Buck变换器中大DCR造成的功率损耗。此外，功率器件的电压应力和电感电流涟漪得到缓解。从而使开关损耗和电导损耗同时得到优化。与以前提出的DPSD变换器相比，建议的T4 DPSD变换器具有负电压开关节点。高摆幅自举门极驱动电路具有增强的电源抑制比（PSRR），即使在最低输入电压下也能将自举电容充电到足够的电压。因此，5A时的满载效率从85%提高到89.3%。当输入电压为2.7 ~ 4.2V，输出电压为1.2V时，峰值转换效率为95.6%。
Type-IV dual-path step-down (T4 DPSD) converter is proposed with conversion efficiency improvement over wide input voltage. The proposed T4 DPSD converter adopts inductor and flying capacitor as power conversion elements, reducing power loss caused by large DCR in conventional Buck converter. Furthermore, the voltage stress of power devices and inductor current ripple are relieved. Thus switching loss and conductance loss are optimized simultaneously. Compared to previously proposed DPSD converters, the proposed T4 DPSD converter features negative voltage switching node. High-swing bootstrap (HSB) gate driver circuit with enhanced PSRR (Power Supply Rejection Ratio) is designed to charge bootstrap capacitor to adequate voltage, even if at lowest input voltage. Consequently, the full load efficiency at 5A is improved from 85% to 89.3%. And the peak conversion efficiency is 95.6% when input voltage is 2.7V to 4.2V with output voltage of 1.2V.