MC2RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference
MC2RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference
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MC2RAM：SRAM 中的马尔可夫链蒙特卡罗采样用于快速贝叶斯推理
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
A. Trivedi
中科院分区：
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作者：
Priyesh Shukla;A. Shylendra;Theja Tulabandhula;A. Trivedi
这项工作讨论了在静态随机存取存储器（SRAM）中从任意高斯混合模型（GMM）进行马尔可夫链蒙特卡罗（MCMC）采样的实现。我们展示了一种新颖的SRAM架构，通过在其中嵌入随机数发生器（RNG）、数模转换器（DAC）和模数转换器（ADC），使得SRAM阵列可用于基于高性能 metropolis - hastings（MH）算法的MCMC采样。大部分昂贵的计算在SRAM内部进行，并且可以并行化以实现高速采样。我们的迭代计算流程在采样过程中使数据移动最小化。我们通过在45纳米CMOS技术上进行模拟来描述我们设计的功耗 - 性能权衡。对于一个二维、两个混合成分的GMM，该实现每次采样迭代消耗约91微瓦的功率，并且在1GHz时钟频率下平均在2000个时钟周期内产生500个样本。我们的研究强调了关于底层硬件非理想性如何影响高层采样特性的有趣见解，并推荐了在面积/功耗限制内优化操作SRAM以实现高性能采样的方法。
This work discusses the implementation of Marko Chain Monte Carlo (MCMC) sampling from an arbitrary Gaussian mixture model (GMM) within SRAM. We show a novel architecture of SRAM by embedding it with random number generators (RNGs), digital-to-analog converters (DACs), and analog-to-digital converters (ADCs) so that SRAM arrays can be used for high performance Metropolis-Hastings (MH) algorithm-based MCMC sampling. Most of the expensive computations are performed within the SRAM and can be parallelized for high speed sampling. Our iterative compute flow minimizes data movement during sampling. We characterize power-performance trade-off of our design by simulating on 45 nm CMOS technology. For a two-dimensional, two mixture GMM, the implementation consumes ∼ 91μW power per sampling iteration and produces 500 samples in 2000 clock cycles on an average at 1 GHz clock frequency. Our study highlights interesting insights on how low-level hardware non-idealities can affect high-level sampling characteristics, and recommends ways to optimally operate SRAM within area/power constraints for high performance sampling.