Towards a Low-SWaP 1024-Beam Digital Array: A 32-Beam Subsystem at 5.8 GHz
Towards a Low-SWaP 1024-Beam Digital Array: A 32-Beam Subsystem at 5.8 GHz
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DOI：
10.1109/tap.2019.2938704
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发表时间：
2020-02
影响因子：
5.7
通讯作者：
A. Madanayake;S. Mandal;T. Rappaport;V. Ariyarathna;Suresh Madishetty;S. Pulipati;R. Cintra;D. Coelho;Raiza Oliviera;F. M. Bayer;L. Belostotski
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作者：
A. Madanayake;S. Mandal;T. Rappaport;V. Ariyarathna;Suresh Madishetty;S. Pulipati;R. Cintra;D. Coelho;Raiza Oliviera;F. M. Bayer;L. Belostotski
毫米波通信需要多波束成形，以利用受障碍物、路径损耗和多径效应影响的无线信道。与模拟相控阵相比，数字多波束形成具有最大的自由度。然而，电路复杂性和功耗是数字多波束系统的重要制约因素。提出了一种低复杂性的数字计算架构，用于近似于多个同时射频（RF）波束的无乘法32点线性变换，类似于离散傅里叶变换（DFT）。由于乘法的算术复杂度从DFT实现的快速傅里叶变换（FFT）复杂度$\mathcal {O}(N\: \log N)$降低到零，因此对于考虑的$N=32$情况，芯片面积和动态功耗分别减少46%和55%。本文描述了使用二维阵列针对1024波束提出的32点DFT近似，并展示了无乘法器近似及其映射到由5.8 GHz天线组成的32波束子系统，该子系统可用于产生1024个数字波束而无需乘法。实时波束计算使用Xilinx现场可编程门阵列（FPGA）实现，每波束带宽为120 MHz。将理论波束性能与定点FFT和所提出的无乘法器算法的测量射频方向图进行了比较，结果吻合良好。
Millimeter-wave communications require multibeam beamforming to utilize wireless channels that suffer from obstructions, path loss, and multipath effects. Digital multibeam beamforming has maximum degrees of freedom compared to analog-phased arrays. However, circuit complexity and power consumption are important constraints for digital multibeam systems. A low-complexity digital computing architecture is proposed for a multiplication-free 32-point linear transform that approximates multiple simultaneous radio frequency (RF) beams similar to a discrete Fourier transform (DFT). Arithmetic complexity due to multiplication is reduced from the fast Fourier transform (FFT) complexity of $\mathcal {O}(N\: \log N)$ for DFT realizations, down to zero, thus yielding a 46% and 55% reduction in chip area and dynamic power consumption, respectively, for the $N=32$ case considered. This article describes the proposed 32-point DFT approximation targeting 1024 beams using a 2-D array and shows the multiplierless approximation and its mapping to a 32-beam subsystem consisting of 5.8 GHz antennas that can be used for generating 1024 digital beams without multiplications. Real-time beam computation is achieved using a Xilinx field-programmable gate array (FPGA) at 120 MHz bandwidth per beam. Theoretical beam performance is compared with measured RF patterns from both a fixed-point FFT and the proposed multiplier-free algorithm and is in good agreement.