Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation
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DOI：
10.1109/tcad.2018.2848590
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发表时间：
2019-08
影响因子：
2.9
通讯作者：
Jun Tao;Yangfeng Su;Dian Zhou;Xuan Zeng;Xin Li
中科院分区：
文献类型：
--
作者：
Jun Tao;Yangfeng Su;Dian Zhou;Xuan Zeng;Xin Li
提出了一种用于模拟电路优化的图约束稀疏性能建模方法。它建立稀疏多项式模型约束的非循环图。这些模型可以用来解决模拟优化问题的局部设计空间内，通过使用凸半定规划松弛有效和鲁棒。我们的数值例子表明，所提出的建模和优化方法可以快速，准确地收敛到一个上级解决方案的模拟电路，而传统的方法无法工作。
In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work.