Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems
Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems
复制标题
DOI：
10.1109/isvlsi49217.2020.00023
复制
发表时间：
2020-07
期刊：
影响因子：
--
通讯作者：
Baogang Zhang;M. G. Sarwar Murshed;Faraz Hussain;Rickard Ewetz
中科院分区：
文献类型：
--
作者：
Baogang Zhang;M. G. Sarwar Murshed;Faraz Hussain;Rickard Ewetz
电阻计算系统（RCSS）预计将被用作深神经网络（DNNS）的推理引擎。不幸的是，由于未成熟的制造过程而导致的设备产量有限，可能会严重降低DNN的分类精度。引起的解决方案是利用有弹性的数据布局组织技术来使用神经网络权重掩盖缺陷。但是，当前技术太慢，无法实现现实世界应用。在本文中，我们为快速弹性吸引的数据布局组织提出了一个框架，以使大型DNN在具有缺陷的RCSS上部署。该框架包含三种加速机制：i）稀疏缺陷索引，ii）重量范围表征和iii）线性编程公式。前两种技术旨在快速计算有关硬件分配（或数据布局组织）的各种数据引入的错误。第三种技术旨在迅速选择导致最小错误量的数据布局组织。实验结果表明，所提出的框架能够在不使用重新培训的情况下实现电阻硬件的软件级别分类精度。与以前的工作相比，平均运行时间减少了89％。
Resistive computing systems (RCSs) are projected to be leveraged as inference engines for Deep Neural Networks (DNNs). Unfortunately, limited device yield due to immature fabrication processes may severely degrade the DNN's classification accuracy. The arising solution is to leverage resilient-aware data layout organization techniques to mask the defects using the neural network weights. However, current techniques are too slow to be practical for real-world applications. In this paper, we propose a framework for fast resilient-aware data layout organization to enable large DNNs to be deployed on RCSs with defects. The framework contains three speed-up mechanisms: i) sparse defect indexing, ii) weight range characterization, and a iii) linear programming formulation. The first two techniques aim to quickly compute the errors introduced by various data to hardware assignments (or data layout organizations). The third technique aims to swiftly select the data layout organization that results in the smallest amount of errors. The experimental results demonstrate that the proposed framework is capable of achieving software level classification accuracy in resistive hardware without any use of retraining. Compared with the previous work, the run-time is reduced with 89% on the average.