Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies
Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies
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DOI：
10.1109/access.2020.3008250
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发表时间：
2020-01-01
期刊：
影响因子：
3.9
通讯作者：
Reisslein, Martin
中科院分区：
文献类型：
--
作者：
Shantharama, Prateek;Thyagaturu, Akhilesh S.;Reisslein, Martin
为了促进灵活的网络服务虚拟化和迁移，网络功能（NFS）越来越多地由软件模块执行，因为通用计算（GPC）平台和基础架构上所谓的“软焊接NFS”。 GPC平台不是专门设计的，可以有效地执行NFS，其典型的输入/输出（I/O）需求。最近，已经开发了许多基于硬件的加速度来增强GPC平台和基础架构，例如中央处理单元（CPU）和内存，以有效地执行NFS。本文全面调查了硬件加速平台和基础架构，以执行软件NFS。该调查涵盖了这两种商业产品，我们认为这是促进技术的，以及相关的研究。我们已经将调查组织为CPU，内存和互连（例如，在CPU和内存之间）以及定制和专用的硬件加速器（嵌入在CPU和内存之间）（例如，在CPU和内存之间）的硬件加速度（例如，在CPU和内存之间）的研究和研究的主要类别（这些都嵌入平台）；此外，我们调查了将GPC平台连接到网络（例如智能网络接口卡）的硬件加速基础架构。我们发现，CPU硬件加速度主要集中在扩展指令集和CPU时钟调整以及缓存相干性上。已经开发了用于片上和芯片连接的硬件加速互连。我们的全面最新调查确定了现有硬件加速平台和基础架构的主要权衡和局限性，用于未来的研究。
In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardware-based accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.