Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
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DOI：
10.1145/968280.968288
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发表时间：
2004-02
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通讯作者：
Fei Li;Yan Lin;Lei He;J. Cong
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作者：
Fei Li;Yan Lin;Lei He;J. Cong
传统的FPGA使用均匀的电源电压Vdd和均匀的阈值电压Vt。我们建议使用预定义的双通道和双Vt结构来降低FPGA功耗。我们设计了具有双通道/双Vt的FPGA电路，以有效地降低动态功耗和泄漏功耗，并在基准电路分析的基础上定义了双通道/双Vt FPGA结构。我们进一步开发CAD算法，包括基于功率灵敏度的电压分配和基于模拟退火的布局，以利用这种结构。与在相同的目标时钟频率下使用均匀的Vdd/Vt的传统结构相比，我们使用双Vt的新结构实现了9%至20%的功耗降低。然而，使用双Vdd和双Vt两者的预定义FPGA结构仅实现平均2%的额外功率降低。这是因为预先设计的双通道布局模式引入了不可忽略的性能损失。因此，需要电源电压的可编程性，以实现显着的节能双芯片FPGA。据我们所知，这是第一次深入研究将双通道和双Vt应用于FPGA，考虑电路，结构和CAD算法。
Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to effectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the pre-defined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the pre-designed dual-Vdd layout pattern introduces non-negligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs. To our best knowledge, it is the first in-depth study on applying both dual-Vdd and dual-Vt to FPGA considering circuits, fabrics and CAD algorithms.