A Novel Technique to Suppress Multiple-Triggering Effect in Typical DTSCRs under ESD Stress
A Novel Technique to Suppress Multiple-Triggering Effect in Typical DTSCRs under ESD Stress
复制标题
一种抑制 ESD 应力下典型 DTSCR 多重触发效应的新技术
DOI：
10.1587/transele.2019ecs6009
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发表时间：
2020-05-01
影响因子：
0.5
通讯作者：
He, Yandong
中科院分区：
文献类型：
--
作者：
Zhang, Lizhong;Wang, Yuan;He, Yandong
本文报道了一种新的技术来抑制典型的二极管触发硅控整流器（DTSCR）中不良的多次触发效应，DTSCR在先进的CMOS技术中经常用作ESD保护元件。该技术的特点是在本征可控硅的N+区下插入额外的N-阱区，这有助于提高衬底电阻。因此，由于所需的触发电流大大降低，并且消除了与多次触发相关的较高触发电压，因此减小了本然可控硅的延迟。新型的DTSCR结构可以改变堆叠二极管的触发电压，以达到精确的触发电压，满足不同的ESD保护要求。所有探索的DTSCR结构都是在65纳米CMOS工艺中制造的。采用传输线脉冲（TLP）和超高速传输线脉冲（VF-TLP）测试系统验证了该技术的有效性，测试结果与分析结果吻合较好。关键词：静电放电，传输线脉冲（TLP），超高速传输线脉冲（VF-TLP），多次触发，二极管触发可控硅整流器（DTSCR）
This work reports a new technique to suppress the undesirable multiple-triggering effect in the typical diode triggered silicon controlled rectifier (DTSCR), which is frequently used as an ESD protection element in the advanced CMOS technologies. The technique is featured by inserting additional N-Well areas under the N+ region of intrinsic SCR, which helps to improve the substrate resistance. As a consequence, the delay of intrinsic SCR is reduced as the required triggering current is largely decreased and multiple-triggering related higher trigger voltage is removed. The novel DTSCR structures can alter the stacked diodes to achieve the precise trigger voltage to meet different ESD protection requirements. All explored DTSCR structures are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and Very-FastTransmission-line-pulsing (VF-TLP) test systems are adopted to confirm the validity of this technique and the test results accord well with our analysis. key words: electrostatic discharge (ESD), transmission-line-pulsing (TLP), very-fast-transmission-line-pulsing (VF-TLP), multiple-triggering, diode-triggered silicon controlled rectifier (DTSCR)