A 19.6 ps, FPGA-Based TDC With Multiple Channels for Open Source Applications
A 19.6 ps, FPGA-Based TDC With Multiple Channels for Open Source Applications
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DOI：
10.1109/tns.2013.2241789
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发表时间：
2013-06-01
影响因子：
1.8
通讯作者：
Charbon, Edoardo
中科院分区：
文献类型：
--
作者：
Fishburn, Matthew W.;Menninga, L. Harmen;Charbon, Edoardo
提出了一种基于现场可编程门阵列（FPGA）的多通道时间数字转换器（TDC）。一个彻底的特征的TDC，基于Xilinx的Virtex-6 FPGA，提出了几个性能参数，包括失真由于FPGA架构，温度效应，芯片内的位置变化，和芯片到芯片的变化。优化后的TDC LSB持续时间为10 ps，积分非线性范围为3.86 LSB，输入范围大于100 μ s。总的时间不确定性（单次抖动）测量为19.6 ps的时间差为40 ns，小于400 ps的时间差大于100 μ s。
This work presents a multi-channel, time-to-digital converter (TDC) based on a field-programmable gate array (FPGA). A thorough characterization of the TDC, based on a Xilinx Virtex-6 FPGA, is presented and several performance parameters are described, including distortions due to the FPGA architecture, temperature effects, intra-chip position variation, and chip-to-chip variation. An optimized TDC exhibits 10 ps LSB duration, an integral non-linearity range of 3.86 LSB, and an input range longer than 100 mu s. Total time uncertainty (single-shot jitter) is measured to be 19.6 ps at a time difference of 40 ns, and less than 400 ps at a time difference larger than 100 mu s.