A FSM Extractor for HDL Description at RTL Level
A FSM Extractor for HDL Description at RTL Level
复制标题
RTL级HDL描述的FSM提取器
DOI：
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复制
发表时间：
2003
期刊：
影响因子：
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通讯作者：
Jing
中科院分区：
文献类型：
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作者：
C. Liu;Jing
Due to the increasing complexity of modern circuit designs, HDL based design methodology is getting popular. Because Finite State Machines (FSMs) and datapaths have significantly different properties, dealing them with two different ways is a trend of many CAD tools. However, how to extract FSMs from the original HDL automatically is still a problem. Furthermore, automatic FSM optimization and converting HDL texts into graphics can be obtained if FSMs in HDL code can be recognized. In this paper, we propose a novel method to recognize FSMs in RTL HDL code and translate them into State Transition Graph (STG). There are almost no restrictions about the writing style of HDLs, except that the HDLs must be synthesizable. No hints or comments in the source codes are needed. The experiments on this algorithm show very promising results.
