Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
复制标题
通过选择性部分设计提取到嵌入式 FPGA 上对硬件加速器进行功能混淆
DOI：
10.1145/3299874.3317992
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
C. Sechen
中科院分区：
文献类型：
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作者：
Bo Hu;Jingxiang Tian;M. Shihab;Gaurav Rajavendra Reddy;W. Swartz;Y. Makris;Benjamin Carrión Schäfer;C. Sechen
知识产权（IP）的保护已成为半导体行业关注的最严重领域之一。为了解决这个问题，我们提出了一种方法和架构来映射设计的选择部分，作为高级综合（HLS）的行为描述，给出高安全性嵌入式现场可编程门阵列（eFPGA）。通过这种方式，只有最终用户才能访问芯片的全部功能。通过六个基准电路，我们证明了我们的方法是有效的。在所有情况下，断开时间（TTB）都很长（至少800万小时），因此在所有实际用途中，设计都是安全的，同时产生约5%的面积开销。此外，延迟只略微增加，而计算时间不到一分钟。
The protection of Intellectual Property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as a behavioral description for High-Level Synthesis (HLS) to a high-security embedded Field-Programmable Gate Array (eFPGA). In this manner, only the end-user has access to the full functionality of the chip. Using six benchmark circuits, we show that our approach is effective. In all cases, the Time-To-Break (TTB) is so long (at least 8 million hours) that for all practical purposes the designs are secure while incurring area overheads of around 5%. Further, latencies were only slightly increased, while the computation times are under one minute.