A Bias-Bounded Digital True Random Number Generator Architecture
A Bias-Bounded Digital True Random Number Generator Architecture
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DOI：
10.1109/tcsi.2016.2606353
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发表时间：
2017-01-01
影响因子：
5.1
通讯作者：
Wong, Hei
中科院分区：
文献类型：
--
作者：
Liu, Yao;Cheung, Ray C. C.;Wong, Hei
偏差现象一直是数字真随机数发生器（TRNG）设计中普遍存在的问题。电路性能可以通过一些辅助模块（例如模拟电路和后处理组件）来提高，这通常也会涉及成本、兼容性、吞吐量和安全性的妥协。在某些情况下，只能实现次优设计。本文利用不同初始状态的不同时序特性，提出了一种能够抑制偏差程度的分阶段运行的自定时环（STR）架构。将所提出的架构与一些使用 Xilinx Zynq-7000 现场可编程门阵列 (FPGA) 平台的传统自由运行架构进行比较，吞吐量为 100 Mbps。随着环尺寸的增加，新提出的结构的偏差程度在小于1%的可忽略水平内；而传统架构的可超过 10%。还进行了统计测试，结果表明，随着初始状态映射的复杂性和所提出结构的环节点的增加，随机性的质量提高。该测试以高 p 值通过了美国国家标准技术研究院 (NIST) 测试套件。
Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values.