A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation
A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation
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0.5V、0.05 至 3.2 GHz、4.1 至 6.4 GHz LC-VCO，使用具有正向体偏置的 E-TSPC 分频器，用于生成亚皮秒抖动时钟
DOI：
10.1109/asscc.2010.5716565
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
A. Matsuzawa
中科院分区：
文献类型：
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作者：
W. Deng;K. Okada;A. Matsuzawa
研究了在未来的0.5V大规模集成电路和节能型大规模集成电路中，采用LC-VCO代替环形压控振荡器产生超低压亚皮秒抖动时钟。提出并实现了一种基于E-TSPC分频技术的0.5V LC-VCO。在测量结果中，获得了0.6ps的抖动，50 MHz到6.4 GHz的2个频段的频率调谐范围和亚LMW PDC的显著性能。
This paper investigates the adoption of LC-VCO to replace ring VCO for ultra-low-voltage sub-picosecond jitter clock generation in future 0.5-V LSI and power aware LSI. A 0.5-V LC-VCO using E-TSPC frequency divider with forward body bias technique is proposed and implemented. Significant performances, in terms of 0.6-ps jitter, 50MHz-to-6.4GHz frequency tuning range with 2 bands and sub-lmW PDC, have been achieved in the measurement results.