A 3Gb/s/wire global on-chip bus with near velocity-of-light latency
A 3Gb/s/wire global on-chip bus with near velocity-of-light latency
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具有接近光速延迟的 3Gb/s/wire 全局片上总线
DOI：
10.1109/vlsid.2006.6
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
C. Svensson
中科院分区：
文献类型：
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作者：
Peter Caputa;C. Svensson
我们成功地展示了一个纯电气全球片上通信链路的实际可行性与近光速延迟。实现的高速链路包括一个5毫米长，全屏蔽，无中继，片上全局总线达到3Gb/s/线在一个标准的0.18/spl亩/米CMOS工艺。传输线式互连通过在较厚的顶部金属M6层中布线信号线并利用金属M4接地返回平面来实现近光速数据传输。线延迟为52.8ps，相当于真空中光速的32%。22%的测量最坏情况下的串扰引起的延迟变化是由电感耦合为主。
We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity-of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18/spl mu/m CMOS process. Transmission-line-style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum. A 22% measured worst-case crosstalk induced delay variation is dominated by inductive coupling.