A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology
A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology
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DOI：
10.1109/jssc.2010.2040117
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发表时间：
2010-03
影响因子：
5.4
通讯作者：
Huaide Wang;Jri Lee
中科院分区：
文献类型：
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作者：
Huaide Wang;Jri Lee
介绍了一种21 Gb/s背板收发器。发射机采用半速率拓扑结构和纯数字模块，大幅降低功耗。接收机采用全速率结构的模拟均衡器和判决反馈均衡器，避免了复杂的结构。单抽头判决反馈均衡器将加法器和限幅器合并到触发器中，缩短了反馈路径，大大加快了运算速度。该收发器采用65 nm CMOS工艺制造，（不包括时钟生成PLL和CDR电路）可在40 cm FR 4通道上提供21 Gb/s数据（231- 1 PRBS），同时在1.2 V电源下功耗为87 mW。
A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate topology with purely digital blocks to substantially reduce power consumption. The receiver employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure. The one-tap decision-feedback equalizer merges the summer and the slicer into the flipflop, shortening the feedback path and speeding up the operation considerably. Fabricated in 65-nm CMOS, the transceiver (excluding clock generating PLL and CDR circuits) delivers 21-Gb/s data (231- 1 PRBS) over 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply.