Simulation Study of Performance for a 20-nm Gate Length In$_{\bf 0.53}$Ga$_{\bf 0.47}$As Implant Free Quantum Well MOSFET
Simulation Study of Performance for a 20-nm Gate Length In$_{\bf 0.53}$Ga$_{\bf 0.47}$As Implant Free Quantum Well MOSFET
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20 nm 栅极长度 In$_{f 0.53}$Ga$_{f 0.47}$As 无注入量子阱 MOSFET 性能仿真研究
DOI：
10.1109/tnano.2012.2199514
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发表时间：
2012
影响因子：
2.4
通讯作者：
Benbakhti B
中科院分区：
文献类型：
--
作者：
Benbakhti B
针对未来高迁移率双沟道CMOS器件，采用新型In0.53Ga0.47As无注入量子阱结构设计了一种nMOSFET器件，实现了低漏电流和高导通电流。它的性能的各个方面进行评估，使用合奏蒙特卡罗技术，校准漂移扩散模拟，和非平衡绿色函数技术。数值研究表明，无注入量子阱nMOSFET具有更好的静电完整性（亚阈值斜率约为80 mV/dec，漏致势垒降低约为40 mV/V），对界面态密度的敏感性低于注入III-V表面沟道结构。我们预测在沟道背面具有δ掺杂的器件具有非常大的驱动电流，并且具有快速的启动。对于没有δ掺杂的器件变体，我们观察到导通电流降低了约30%，并且由于缺乏载流子，横向间隔物（访问区域）的厚度对驱动电流有很大的影响。最后，沟道厚度的减小导致当沟道收缩到2nm时，较高的谷对总电流的贡献从4%增加到25%。
An nMOSFET for the future high mobility dual-channel CMOS based on anew In0.53Ga0.47As implant free quantum well architecture is optimized to achieve low leakage and high on-current. Various aspects of its performance are evaluated using the ensemble Monte Carlo technique, calibrated drift-diffusion simulations, and non-equilibrium Green's functions technique. The numerical investigations demonstrate that the implant-free quantum-well nMOSFET has a better electrostatic integrity (a subthreshold slope of ~80 mV/dec and a drain induced barrier lowering of ~40 mV/V) and less sensitivity to the interface states density than the implanted III-V surface channel architectures. We predict a very large drive current with a swift onset for the device with δ-doping on the backside of the channel. For the device variant without δ-doping, we observe the on-current reduction by about 30% and a large influence of thickness of lateral spacers (access regions) on the drive current due to the lack of carriers. Finally, the decrease in the channel thickness results in the increase of a higher valleys contribution into the total current from 4% to 25% when the channel is shrunk from to 2 nm.